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low cost, triple differential drivers for wideband video ad8141/ad8142 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features triple, high speed differential drivers 255 mhz, ?3 db large signal bandwidth 65 mhz, 0.1 db flatness 1150 v/s slew rate 12 ns settling time single 5 v or split supply operation fixed gain of 2 internal common-mode feedback network output balance error ?50 db at 50 mhz ad8142 has integrated sync-on-common-mode circuitry high-z output when disabled differential-to-differential or single-ended-to-differential operation high isolation between amplifiers: ?100 db at 10 mhz low power: 44 ma at 5 v available in space-saving packaging: 4 mm 4 mm lfcsp applications keyboard-video-mouse (kvm) networking video distribution digital signage security cameras general description the ad8141 and ad8142 are triple, low cost, differential or single-ended-input-to-differential-output drivers. each amplifier has a fixed gain of 2 to compensate for the attenuation of the line termination resistors. the ad8141 and ad8142 are specifically designed for rgb signals but can be used for any type of signals. the amplifiers have very fast slew rate and settling time while being manufactured on a cost effective cmos process. they are optimized for high resolution video performance with a 0.1 db flatness of 65 mhz, which allows driving high resolution video over any type of utp cable. the drivers have an internal common-mode feedback loop that provides output amplitude and phase matching, achieving ?50 db balance error at 50 mhz and thereby suppressing even- order harmonics and minimizing radiated electromagnetic interference (emi). functional block diagrams 09461-001 1 dis 2 v s? /gnd 3 ?in a 4 +in a 5 v s? /gnd 6 ?out a +out a v s+ +out b ?out b v s+ +out c 15 +in c 16 ?in c 17 v s+ 18 24 23 22 21 20 19 v ocm c 14 v s? /gnd 13 121110 987 ?out c v s? /gnd +in b ?in b v s+ v ocm a v ocm b + ? + ? + ? ad8141 figure 1. 09461-002 +out r v s+ +out g ?out g v s+ +out b 24 23 22 21 20 19 1211 10 987 v s? /gnd +in g ?in g v s+ v sync h sync + ? + ? + ? ad8142 15 16 17 18 14 13 1 2 3 4 5 6 dis v s? /gnd ?in r +in r v s? /gnd ?out r +in b ?in b v s+ sync level v s? /gnd ?out b 2 figure 2. the ad8142 includes a unique sync-on-common-mode feature that allows the user to transmit balanced horizontal and vertical video sync signals over the three common-mode channels. additionally, the ad8141 and ad8142 both have a disable feature that, when asserted, produces high-z outputs, allowing line isolation and easy multiplexing. the ad8141 and ad8142 are available in a 24-lead 4 mm 4 mm lfcsp and operate over a temperature range of ?40c to +85c. they can be used with the ad8145 triple differential-to-single- ended receiver, ad8123 triple equalizer, ad8120 triple delay line, and the ad8117 or ad8175 crosspoint switches to produce a high resolution video distribution system.
ad8141/ad8142 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? thermal resistance ...................................................................... 5 ? maximum power dissipation ..................................................... 5 ? esd caution.................................................................................. 5 ? pin configurations and function descriptions ........................... 6 ? typical performance characteristics ............................................. 8 ? basic test circuit ........................................................................ 13 ? terminology .................................................................................... 14 ? theory of operation ...................................................................... 15 ? analyzing an application circuit............................................. 15 ? closed-loop gain ...................................................................... 15 ? calculating an application circuits input impedance ......... 15 ? input common-mode voltage range in single-supply applications ................................................................................ 16 ? terminating a single-ended input .......................................... 16 ? driving a capacitive load......................................................... 17 ? disable ......................................................................................... 17 ? ad8142 sync-on-common-mode......................................... 17 ? applications information .............................................................. 18 ? driving rgb video over cat-5 cable .................................... 18 ? single 5 v supply application information............................ 19 ? ad8142 signal levels on various supplies ............................ 20 ? disable feature ........................................................................... 20 ? driving multiple outputs.......................................................... 21 ? video sync-on-common-mode (ad8142) .......................... 21 ? layout and power supply decoupling considerations......... 22 ? amplifier-to-amplifier isolation ............................................. 22 ? exposed paddle (epad)............................................................ 22 ? typical ad8142 5 v application circuit................................ 23 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history 7 /11revision 0: initial version
ad8141/ad8142 rev. 0 | page 3 of 24 specifications v s+ = 5 v, v s? = 0 v, r l, dm = 200 , t a = 25c, v ocm = 1.5 v ( ad8141 ), h sync , v sync , and sync level = 0 v ( ad8142 ), unless otherwise noted. table 1. parameter test conditions/comments min typ max unit differential input performance dynamic performance ?3 db small signal bandwidth v o = 0.2 v p-p, ad8141/ ad8142 275/285 mhz ?3 db large signal bandwidth v o = 2 v p-p, ad8141/ ad8142 255/265 mhz bandwidth for 0.1 db flatness v o = 2 v p-p 65 mhz slew rate v o = 2 v p-p, 25% to 75% (rise/fall) 1150/1250 v/s settling time to 0.1% v o = 2 v step 12 ns isolation between amplifiers f = 10 mhz, between amplifier r and amplifier g ?100 db differential input characteristics input common-mode voltage range v ocm = v s+ /2 v s? + 0.2 v s+ ? 1 v input resistance differential 2 k single-ended input 1.5 k input capacitance differential 2 pf dc cmrr v out, dm /v in, cm , v in, cm = 1 v ?60 db differential output characteristics differential signal gain v out, dm /v in, dm , v in, dm = 1 v 1.95 2 2.04 v/v output voltage swing each single-ended output v s? + 0.18 v s+ ? 0.4 v output offset voltage ?70 1.5 +70 mv output offset drift t min to t max 30 v/c output balance error f = 50 mhz ?50 db dc ?66 ?43 db output voltage noise (rto) f = 20 mhz 41 nv/hz maximum number of parallel loads 1.4 v p-p into 200 per load 4 loads common-mode input performance (ad8141) v ocm dynamic performance ?3 db bandwidth v ocm = 100 mv p-p 114 mhz slew rate v ocm = 0.5 v to 2.5 v, 25% to 75% (rise/fall) 130/155 v/s dc gain v ocm = 1 v 0.98 1.00 1.02 v/v v ocm input characteristics input voltage range v s? + 0.2 v s+ ? 0.2 v input resistance thevenin to midsupply 2.8 k input offset voltage ?87 ?30 +26 mv dc cmrr v out, dm /v ocm ; v ocm = 1 v ?60 db common-mode sync performance (ad8142) slew rate v out, cm = 0.5 v to +2.5 v; 25% to 75% (rise/fall) 130/155 v/s nominal output common-mode level v s? + 1.5 v h sync and v sync inputs (ad8142) input low voltage referenced to gnd 0 to 1.6 v input high voltage referenced to gnd 1.9 to 5 v sync level input (ad8142) input voltage range referenced to v s? v s? v s? + 1 v setting to achieve 0.5 v pulse levels referenced to v s? v s? + 0.5 v gain to red common-mode output v out, cm /v sync level 0.85 1.00 1.15 v/v gain to green common-mode output v out, cm /v sync level 1.8 2.00 1.2 v/v gain to blue common-mode output v out, cm /v sync level ?1.15 ?1.00 ?0.85 v/v
ad8141/ad8142 rev. 0 | page 4 of 24 parameter test conditions/comments min typ max unit power supply operating range positive supply 4.5 5.5 v quiescent current ad8141 / ad8142 44/47 56/57 ma disabled 1.2 1.6 ma psrr ?77 db output high-z performance dis input low voltage 0 to 1.6 v dis input high voltage 1.9 to v s+ v dis assert time 5 ns dis deassert time 50 ns differential output impedance magnitude with dis asserted 1 mhz, each output, dis input at v s+ 11 k 10 mhz, each output, dis input at v s+ 1.9 k isolation input-to-output 1 mhz, each output, dis input at v s+ ?78 db 10 mhz, each output, dis input at v s+ ?58 db
ad8141/ad8142 rev. 0 | page 5 of 24 absolute maximum ratings table 2. parameter rating supply voltage 5.5 v h sync , v sync , sync level v s? /v s+ power dissipation see figure 3 input common-mode voltage v s? /v s+ storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the load current consists of differential and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and common-mode feedback loops. the internal resistor tap used in the common- mode feedback loop places a 12.5 k differential load on the output. rms output voltages should be considered when dealing with ac signals. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the ja . the exposed pad on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a pcb plane to achieve the specified ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 24-lead lfcsp (38c/w) on a jedec standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a pcb plane. ja values are approximations. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for the device soldered in a circuit board in still air. 0 1 2 3 4 5 6 ?40 ?20 0 20 40 60 80 maximum power dissipation (w) ambient temperature (c) 09461-055 table 3. thermal resistance with the underside pad thermally connected to a copper plane package type/pcb type ja jc unit 24-lead lfcsp/4-layer 38 4.7 c/w maximum power dissipation the maximum safe power dissipation in the ad8141/ ad8142 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8141 / ad8142 . exceeding a junction temperature of 175c for an extended period can result in changes in the silicon devices potentially causing failure. figure 3. maximum power dissipation vs. temperature for a 4-layer board esd caution
ad8141/ad8142 rev. 0 | page 6 of 24 pin configurations and function descriptions pin 1 indicator 1 dis 2 v s? /gnd 3 ?in a 4 +in a 5 v s? /gnd 6 ?out a +out a v s+ +out b ?out b v s+ +out c 15 +in c 16 ?in c 17 v s+ 18 v ocm c 14 v s? /gnd 13 ?out c notes 1. connect exposed paddle to ground. v s? /gn d +in b ?in b v s+ v ocm a v ocm b 7 8 9 11 21 01 12 22 32 42 02 91 ad8141 top view (not to scale) 09461-004 figure 4. ad8141 pin configuration table 4. ad8141 pin function descriptions pin o. nemonic description 1 dis disable. this pin places outputs in hi gh-z condition and lowers supply current. 2, 5, 14, 21 v s? /gnd negative power supply voltage. 3 ?in a inverting input, amplifier a. 4 +in a noninverting input, amplifier a. 6 ?out a negative output, amplifier a. 7 +out a positive output, amplifier a. 8, 11, 17, 24 v s+ positive power supply voltage. 9 +out b positive output, amplifier b. 10 ?out b negative output, amplifier b. 12 +out c positive output, amplifier c. 13 ?out c negative output, amplifier c. 15 +in c noninverting input, amplifier c. 16 ?in c inverting input, amplifier c. 18 v ocm c the voltage applied to this pin controls th e output common-mode voltage for amplifier c. 19 v ocm b the voltage applied to this pin controls th e output common-mode voltage for amplifier b. 20 v ocm a the voltage applied to this pin controls th e output common-mode voltage for amplifier a. 22 +in b noninverting input, amplifier b. 23 ?in b inverting input, amplifier b. epad connect exposed paddle to ground.
ad8141/ad8142 rev. 0 | page 7 of 24 pin 1 indicator 1 dis 2 v s? /gnd 3 ?in r 4 +in r 5 v s? /gnd 6 ?out r +out r v s+ +out g ?out g v s+ +out b 15 +in b 16 ?in b 17 v s+ 18 sync level 14 v s? /gnd 13 ?out b v s? /gn d +in g ?in g v s+ v sync h sync 7 8 9 11 21 01 12 22 32 42 02 91 ad8142 top view (not to scale) 09461-005 notes 1. connect exposed paddle to ground. figure 5. ad8142 pin configuration table 5. ad8142 pin function descriptions pin o. nemonic description 1 dis disable. this pin places outputs in hi gh-z condition and lowers supply current. 2, 5, 14, 21 v s? /gnd negative power supply voltage. gnd is for single 5 v applications. 3 ?in r inverting input, red amplifier. 4 +in r noninverting input, red amplifier. 6 ?out r negative output, red amplifier. 7 +out r positive output, red amplifier. 8, 11, 17, 24 v s+ positive power supply voltage. 9 +out g positive output, green amplifier. 10 ?out g negative output, green amplifier. 12 +out b positive output, blue amplifier. 13 ?out b negative output, blue amplifier. 15 +in b noninverting input, blue amplifier. 16 ?in b inverting input, blue amplifier. 18 sync level the voltage applied to this pin with respect to v s? /gnd controls the amplitude of the sync pulses that are applied to the common-mode voltages. 19 h sync horizontal sync pulse input with respect to ground. 20 v sync vertical sync pulse input with respect to ground. 22 +in g noninverting input, green amplifier. 23 ?in g inverting input, green amplifier. epad connect exposed paddle to ground.
ad8141/ad8142 rev. 0 | page 8 of 24 typical performance characteristics v s+ = 5 v, v s? = 0 v, r l, dm = 200 , t a = 25c, v ocm = 1.5 v ( ad8141 ), h sync , v sync , and sync level = 0 v ( ad8142 ), unless otherwise noted. 9 6 3 0 ?3 ?6 1 10 100 1k frequency (mhz) gain (db) 09461-007 v out, dm = 200mv p-p ad8141 ad8142 figure 6. small signal frequency response 9 6 3 0 ?3 ?6 ?9 ?12 1 10 100 1k frequency (mhz) gain (db) 09461-008 v out, dm = 200mv p-p figure 7. small signal frequency response at v ocm = 2.5 v ( ad8141 ) 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 1 10 100 1k frequency (mhz) gain (db) 09461-009 v out, dm = 200mv p-p ad8141 ad8142 figure 8. small signal 0.1 db flatness 9 6 3 0 ?3 ?6 1 10 100 1k frequency (mhz) gain (db) 09461-010 v out, dm = 2v p-p ad8141 ad8142 figure 9. large signal frequency response 9 6 3 0 ?3 ?6 ?9 ?12 1 10 100 1k frequency (mhz) gain (db) 09461-011 v out, dm = 2v p-p figure 10. large signal frequency response at v ocm = 2.5 v ( ad8141 ) 6.7 6.6 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 1 10 100 1k frequency (mhz) gain (db) 09461-012 v out, dm = 2v p-p ad8141 ad8142 figure 11. large signal 0.1 db flatness
ad8141/ad8142 rev. 0 | page 9 of 24 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 1 10 100 1k frequency (mhz) output balance error (db) 09461-013 ? v out, cm / ? v out, dm ? v out, dm = 2v p-p figure 12. output bala nce error vs. frequency ? 30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0.1 1 10 100 frequency (mhz) distortion (dbc) 09461-014 v out, dm = 2v p-p hd3 hd2 figure 13. ad8141 harmonic distortion vs. frequency ? 20 ?40 ?60 ?80 ?100 ?120 ?140 11 0 frequency (mhz) 100 1k isolation (db) 09461-015 green to red, ? v out, dm r/ ? v in, dm g red figure 14. channel-to-channel isolation vs. frequency 100k 10k 1k 100 10 10 100 1k 10k 100k 1m 10m 100m frequency (hz) output noise (nv/ hz) 09461-016 figure 15. output voltage noise density vs. frequency ? 30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 100 frequency (mhz) distortion (dbc) 09461-017 v out, dm = 2v p-p hd3 hd2 figure 16. ad8142 harmonic distortion vs. frequency ? 30 ?40 ?50 ?60 ?70 ?80 ?90 1 10 100 1k frequency (mhz) isolation (db) 09461-018 dis input voltage = 5v figure 17. disabled input-to-o utput isolation vs. frequency
ad8141/ad8142 rev. 0 | page 10 of 24 ? 20 ?30 ?40 ?50 ?60 ?70 1 10 100 1k frequency (mhz) common-mode rejection (db) 09461-019 ? v out, dm / ? v in, cm ? v in, cm = 1v p-p figure 18. common-mode rejection vs. frequency 100k 10k 1k 100 10 1 10 100 1k frequency (mhz) differential output impedance magnitude ( ? ) 09461-020 directly at driver output figure 19. disabled output impedance magnitude vs. frequency 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 0 5 10 15 20 25 30 35 40 45 50 time (ns) differential output voltage (v) 09461-021 ad8141 ad8142 figure 20. small signal transient response ? 30 ?40 ?50 ?60 ?70 ?80 ?90 1 10 100 1k frequency (mhz) power supply rejection (db) 09461-022 2.5v supplies ? supply = 0.5v ad8141 v s + ad8141 v s ? ad8142 v s + ad8142 v s ? figure 21. power supply rejection vs. frequency ?5 0 5 10 15 20 25 30 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 40 80 120 160 200 240 280 320 360 400 dis pin voltage (v) differenti a l output voltage (v) time (ns) v s+ = +2.5v v s? = ?2.5v v in = 0.7v dc v ocm = gnd dis pin differential output 09461-051 figure 22. disable response time 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 5 10 15 20 25 30 35 40 45 50 time (ns) differential output voltage (v) 09461-024 ad8141 ad8142 figure 23. large signal transient response
ad8141/ad8142 rev. 0 | page 11 of 24 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 0 5 10 15 20 25 30 35 40 45 50 time (ns) differential output voltage (v) 09461-025 figure 24. small signal transient response, v ocm = 2.5 v ( ad8141 ) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 ?4 0 4 8 12162024283236 settling error voltage (mv) input and output voltage (v) time (ns) input output error 0.1% settled point 0.5% settled point 09461-054 figure 25. differential settling time 58 56 54 52 50 48 46 44 42 40 38 ?40 ?20 0 20 40 60 80 100 temperature (c) power supply current (ma) 09461-027 r l, dm = open circuit ad8141 ad8142 figure 26. positive power supply current vs. temperature 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 5 10 15 20 25 30 35 40 45 50 time (ns) differential output voltage (v) 09461-028 figure 27. large signal transient response, v ocm = 2.5 v ( ad8141 ) 7 6 5 4 3 2 1 0 ?7 ?2 ?3 ?4 ?5 ?6 ?1 0 100 200 300 400 500 600 700 800 900 1000 time (ns) differential voltage (v) 09461-029 v s+ = +2.5v v s? = ?2.5v v ocm = 0v single-ended drive 2 input v out _diff figure 28. ad8141 differential overdrive recovery ? 35 ?37 ?39 ?41 ?43 ?45 ?47 ?49 ?51 ?53 ?40 ?20 0 20 40 60 80 100 temperature (c) power supply current (ma) 09461-030 r l, dm = open circuit ad8141 ad8142 figure 29. negative power su pply current vs. temperature
ad8141/ad8142 rev. 0 | page 12 of 24 4.85 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 4.80 4.75 4.70 4.65 4.60 4.55 4.50 ?40 ?20 0 20 40 60 80 100 temperature (c) positive output saturation voltage (v) negative output saturation voltage (v) 09461-031 single-ended output voltage positive swing negative swing figure 30. output satu ration vs. temperature 3 0 ?3 ?6 ?9 ?12 1 10 100 1k frequency (mhz) gain (db) 09461-032 ? v out, cm / ? v ocm v out, cm = 100mv p-p figure 31. v ocm frequency response ( ad8141 ) 4.0 3.5 3.0 2.5 2.0 0 1.5 1.0 0.5 0 102030405060708090100 time (ns) differential output voltage (v) 09461-033 v s+ = 5v v s? = 0v v ocm = 2.5v v ocm = 1.5v figure 32. v ocm large signal transient response ( ad8141 ) ? 40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 1 10 100 1k frequency (mhz) v ocm common-mode rejection (db) 09461-044 ? v out, dm / ? v ocm ? v ocm = 2v p-p figure 33. v ocm common-mode rejection vs. frequency
ad8141/ad8142 rev. 0 | page 13 of 24 ?2.5 2.5 7.5 12.5 17.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 0 102030405060708090100 time (ns) sync input voltage (v) channel output common-mode voltage (v) 09461-050 r cm g cm b cm h sync v sync sync level = 0.5v figure 34. ad8142 output common-mode signals for various sync pulse inputs basic test circuit 09461-006 1k? 50 ? 2k? +5 v 1k? 50 ? 2k? ad8141/ad8142 r l, dm 200 ? v out, dm v s? v s+ ? + v test 52.3 ? 52.3 ? 0.1f on all v s+ pins midsupply test signal source figure 35. basic test circuit
ad8141/ad8142 rev. 0 | page 14 of 24 terminology differential voltage output balance output balance is a measure of how well the differential output signals are matched in amplitude and how close they are to exactly 180 apart in phase. balance can be easily determined by placing a well-matched resistor divider between the differential output voltage nodes and comparing the magnitude of the signal at the dividers midpoint with the magnitude of the differential signal. by this definition, output balance error is the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differential-mode voltage in response to a differential input signal. differential voltage refers to the difference between two node voltages that are balanced with respect to each other. for example, in figure 36 , the output differential voltage (or output differential mode voltage) is defined as v out, dm = ( v op ? v on ) common-mode voltage refers to the average of two node voltages with respect to a common reference (usually the local ground). the output common-mode voltage is defined as 2 )( , on op cmout vv v + = dm out cm out v v error balance output , , =
ad8141/ad8142 rev. 0 | page 15 of 24 theory of operation the differential drivers contained in the ad8141 and ad8142 differ from conventional op amps in that they have two outputs whose voltages move in opposite directions. like op amps, they rely on high open-loop gain and negative feedback to force these outputs to the desired voltages. the ad8141 and ad8142 drivers make it easy to perform single-ended-to-differential conversion, common-mode level-shifting, and amplification of differential signals. previous differential drivers, both discrete and integrated designs, have been based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. when these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. achieving a balanced output has generally required exceptional matching of the amplifiers and feedback networks. dc common-mode level-shifting has also been difficult with previous differential drivers. level-shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. sometimes, the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. excellent performance over a wide frequency range has proven difficult with this approach. each ad8141 / ad8142 driver uses two feedback loops to separately control the differential and common-mode output voltages. the differential feedback, set by the internal resistors, controls the differential output voltage only. the internal common- mode feedback loop controls the common-mode output voltage only. this architecture makes it easy to arbitrarily set the output common-mode level by simply applying a voltage to the v ocm input. the output common-mode voltage is forced, by internal common-mode feedback, to equal the voltage applied to the v ocm input, while simultaneously balancing the differential output voltage. the ad8141 v ocm inputs are available to the user, whereas the ad8142 v ocm inputs are internally connected to sync-on-common- mode circuitry that automatically imbeds the h sync and v sync signals on the three output common-mode voltages. the overall driver architecture produces outputs that are highly balanced over a wide frequency range without requiring external components or adjustments. the common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. the result is nearly perfectly balanced differential outputs of identical amplitude that are 180 apart in phase. analyzing an application circuit the drivers use two negative feedback loops, each with high open-loop gain, to force their differential and common-mode output voltages in such a way as to minimize the differential and common-mode input error voltages. the differential input error voltage is defined as the voltage between the differential inputs labeled v ap and v an in figure 36 . for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common-mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. closed-loop gain the differential mode gain of the circuit in figure 36 can be described by 2 == g f dmin, dmout, r r v v where r f = 2.0 k and r g = 1.0 k nominally. 09461-034 r f r g v ap v an r g r f r l, dm v out, dm v on v op v ocm v in, dm v ip v in + ? figure 36. circuit definitions calculating an application circuits input impedance the effective input impedance of a circuit such as that in figure 36 at v ip and v in depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, the differential input impedance, r in, dm between the inputs v ip and v in is simply r in, dm = 2 r g = 2.0 k in the case of a single-ended input signal (for example, if v in is grounded and the input signal is applied to v ip ), the input impedance becomes () k 5.1 2 1 = ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g in rr r r r the input impedance of the circuit is higher than for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g .
ad8141/ad8142 rev. 0 | page 16 of 24 input common-mode voltage range in single-supply applications the driver inputs are designed to facilitate level-shifting of ground referenced input signals on a single power supply. for a single- ended input, this implies, for example, that the voltage at v in in figure 36 is 0 v when the amplifiers negative power supply voltage is also set to 0 v. it is important to ensure that the common-mode voltage at the amplifier inputs, v ap and v an , stays within its specified range. because the v ap and v an voltages are driven to be essentially equal by negative feedback, the amplifiers input common-mode voltage can be expressed as a single term, v acm . v acm can be calculated as 3 2 icm ocm acm vv v + = where v icm is the common-mode voltage of the input signal, that is, 2 inip icm vv v + = terminating a single-ended input each driver has a nominal fixed gain of 2, with r f = 2.0 k and r g = 1.0 k. a typical single-ended video signal source applied to the ad8141 / ad8142 input has a maximum terminated output voltage of 0.7 v p-p and source resistance of 75 . because the terminated output voltage of the source is 0.7 v p-p, the open- circuit output voltage of the source is 1.4 v p-p. the source shown in figure 37 indicates this open-circuit voltage. the following three steps illustrate how to terminate a signal from a typical single-ended 75 video source. 1. the single-ended input impedance is calculated as r in = 1.5 k. ad8141/ ad8142 r l +5v v out, dm + ? video source r in 1.5k ? 0 9461-035 r g 1k? r f 2k? r f 2k? r g 1k? r s 75? v s 1.4v p-p figure 37. calculating single -ended input impedance, r in 2. to match the 75 source resistance, the termination resistor, r t , is calculated using r t ||1.125 k = 75 . the closest standard 1% value for r t is 80.6 . ad8141/ ad8142 r l +v s ?v s v out, dm + ? r in 75 ? 09461-036 r t 80.6 ? r g 1k ? r g 1k ? r s 75? r f 2k? r f 2k ? v s 1.4v p-p figure 38. adding termination resistor r t 3. it can be seen from figure 38 that the effective r g in the upper feedback loop is now greater than the r g in the lower loop due to the addition of the termination resistors. to compensate for the imbalance of the gain resistors, a correction resistor (r ts ) is added in series with r g in the lower loop. r ts is the closest 1% resistor to the thevenin equivalent of the source resistance r s and the termination resistance r t , equal to r s ||r t . 09461-037 r t 80.6 ? r s 75 ? r th 38.8 ? v th 0.725v p-p v s 1.4v p-p figure 39. calculating the thevenin equivalent r th = r s ||r t = 38.8 , and r ts = 38.3 . note that v th is greater than 0.7 v p-p, which was obtained with r t = 75 alone. the modified circuit with the thevenin equivalent of the terminated source and r ts in the lower feedback loop is shown in figure 40 . ad8141/ ad8142 r l +v s ?v s v out, dm + ? 09461-038 r ts 38.3 ? r f 2k? r g 1k? r g 1k? r th 38.8 ? r f 2k ? v th 0.725v p-p figure 40. thevenin equivalent and matched gain resistors figure 40 presents a tractable circuit with matched feedback loops that can be easily evaluated. it is useful to point out two effects that occur with a terminated input. the first is that the value of r g is increased in both loops, lowering the overall closed-loop gain. the second is that v th is a little larger than 0.7 v p-p, as it is if r t = 75 alone. these two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops, the effects essentially cancel each other out. for smaller r f and r g , however, the diminished closed-loop gain is not canceled completely by the increased v th .
ad8141/ad8142 rev. 0 | page 17 of 24 the desired differential output in this example is 1.4 v p-p because the terminated input signal is 0.7 v p-p and the closed- loop gain = 2. the actual differential output voltage is equal to (0.725 v p-p)(2 k/1038.3 ) = 1.4 v p-p. this illustrates how the two aforementioned effects cancel for large r f and r g . ad8142 sync-on-common-mode the ad8142 includes on-chip, sync-on-common-mode circuitry that encodes externally applied h sync and v sync signals onto the common-mode output voltages of each of the r, g, and b drivers. the circuit encodes the horizontal and vertical sync pulses in a way that results in low radiated energy. a simplified circuit that illustrates how the pulses are encoded is shown in figure 41 . for a more detailed description of the sync scheme, see the applications information section. driving a capacitive load a purely capacitive load can react with the output impedance of the drivers to reduce phase margin, resulting in high frequency ringing in the pulse response. the best way to minimize this effect is to place the source termination resistors immediately at the amplifier outputs to minimize parasitic capacitances formed by unnecessarily long traces. the sync-on-common-mode circuit generates a current based on the voltage applied to the sync level input pin (pin 18) with respect to the negative supply. with sync level input tied to v s? , the common-mode output of all drivers is set at 1.5 v above the negative supply. using a resistor divider, a voltage can be applied between v s? and sync level that determines the maximum deviation of the common-mode outputs from their midsupply level. if, for instance, sync level ? v s? = 0.5 v and the supply voltage is 5 v, then the common-mode outputs fall within an envelope of 1.5 v 0.5 v. the state of each v out, cm output based on the h sync and v sync inputs is determined by the equations defined in the applications information section. disable the ad8141 and ad8142 have disable pins that, when pulled high, significantly reduce the power consumed while simultaneously placing the outputs in high-z states. the disable feature can be used to multiplex two drivers. see figure 17 , figure 19 , and figure 22 for the disabled input-to-output isolation, output impedance, and response performance. the threshold levels for the disable pin are listed in table 1 . an output glitch occurs whenever the disable feature is asserted or deasserted. see the applications information section for details. for the positive supplies between 2.5 v and 5 v, the sync-on- common-mode circuit can be used by directly applying standard h sync and v sync signals to the respective ad8142 inputs. these inputs adhere to standard logic thresholds (see table 1 for the exact levels). the h sync and v sync inputs, therefore, can be driven directly off the output of a computer video card without concern of being overdriven. the input path from the h sync and v sync inputs to the switches in the current mode level-shifting circuit are well matched to eliminate false switching transients. this maximizes common-mode balance and minimizes radiated energy. h v v h hr r r r r r h v v s? blue v ocm sync level h sync v sync v s+ h v h r v mirror mirror v v v red v ocm green v ocm 09461-039 figure 41. sync-on-common-mode simplified circuit
ad8141/ad8142 rev. 0 | page 18 of 24 applications information driving rgb video over cat-5 cable the ad8141 and ad8142 are devices whose foremost application is driving rgb and component video signals over unshielded twisted pair (utp) cable in video distribution networks. single- ended video signals are easily converted to differential signals for transmission over the cable, and the internally fixed gain of 2 automatically compensates for the losses incurred by the source and load terminations. figure 42 shows the ad8141/ ad8142 in a triple, single-ended-to-differential application when driven from a 75 video source. ad8141/ad8142 + ? r 1k? 1k? 2k? 2k? 49.9 ? 49.9 ? 75? 38.3 ? 80.6 ? red video source red utp + ? g 1k? 1k? 2k? 2k? 49.9 ? 49.9 ? 75? 38.3 ? 80.6 ? green video source green utp + ? b 1k? 1k? 2k? 2k? 49.9 ? 49.9 ? 75? 38.3 ? 80.6 ? blue video source blue utp disable dis v s? v s? +5 v 0.1f on all v s+ pins 09461-040 figure 42. ad8141 / ad8142 in single-ended-to-differential application on sing le 5 v supply (sync pulse encoding not shown)
ad8141/ad8142 rev. 0 | page 19 of 24 single 5 v supply application information the ad8141 and ad8142 require a nominal voltage of 5 v across their v s+ and v s? power supply pins, and that their epads be connected to system ground; the voltage between v s+ and the local system ground must be greater than or equal to 2.5 v and less than or equal to 5 v. these requirements can be met by a single +5 v supply, or split supplies such as 2.5 v, +3 v/?2 v, and so on. operating the ad8141 and ad8142 with 2.5 v supplies provides considerable power savings compared with other drivers operating at 5 v supplies, without any disadvantages with regard to input and output ranges in most cases. the receivers used with the ad8141 and ad8142 , such as the ad8145, ad8143 , ad8123, and ad8128, generally operate with split supplies, ranging from 5 v to 12 v. the split supply arrangement results in a receiver input common-mode range that is centered at 0 v relative to the local ground reference and ranges to within a volt or two from each rail. ground potential differences normally exist between the driver end and the receiver end, and these differences cause the relative common-mode voltages between the driver and receiver to shift. see figure 43 for an example. in figure 43 , v r, cm = v o, cm + v shift . if v o, cm = 0 v and v shift = 2 v, v r, cm is 2 v. this is because the receiver ground is shifted down by 2 v relative to the driver ground, and the common- mode level on the cable stays constant. it can be seen from this example that the most margin to absorb ground shifts exists when the center of the receiver input common-mode voltage range relative to its ground is the same as the output common- mode voltage of the driver with respect to its ground. most receivers operate with their input common-mode ranges centered at 0 v; therefore, the best case for the driver is to set its output common-mode voltage to 0 v. this is not possible for the ad8141 or ad8142 on a single 5 v supply, but can be accomplished using split supplies. if a single 5 v supply is required, the rail- to-rail output allows the ad8141 output common-mode voltage to be set to less than 1 v to be as close as possible to the ideal setting of 0 v. whereas the ad8141 has uncommitted v ocm inputs, the ad8142 has internal sync-encoding circuitry that fixes the nominal output common-mode voltage at 1.5 v above the negative rail. each part has a resistive divider on the v ocm input that sets the nominal output common-mode voltage to 1.5 v above the negative rail when no external voltage is applied. the divider consists of a 8.75 k resistor to v s+ and a 3.75 k resistor to v s? , forming a thevenin equivalent load of 2.6 k to 30% of the voltage across the supplies. in the single 5 v supply case, the thevenin load voltage is 30% of 5 v above 0 v, or 1.5 v. + ? 09461-041 100 ? 49.9 ? driver 100 ? utp 49.9 ? + v r, cm ? + v o, cm ? + ? v shift + ? v ocm ad8141/ad8142 figure 43. end-to-end common-mode shifts due to ground shifts
ad8141/ad8142 rev. 0 | page 20 of 24 ad8142 signal levels on various supplies figure 44 and figure 45 illustrate the key video signal levels seen in typical applications operating on a single +5 v supply and 2.5 v supplies; common-mode sync pulses are omitted from the circuit drawing for clarity but are shown in a separate waveform drawing of the signals directly at the ad8142 outputs, shown just below the associated circuit drawing. the sync pulses are common-mode, that is, they move in the same direction on each output polarity. in figure 44 and figure 45 , this means that the h sync pulses are either both green or both blue for the red and black video signals. disable feature when asserted, the disable feature minimizes quiescent current consumption and provides a high-z output. it offers a convenient means to connect two driver outputs together in parallel to form a tristate multiplexed application. the disable feature can also be used to minimize quiescent current drawn when a particular device is not being used. the disable pin is a binary input that controls the state of the ad8141/ ad8142 outputs. its binary input levels are compatible with most ttl and cmos families (see table 1 for the logic levels). the ad8141/ ad8142 output is disabled when the disable input is driven to its high state, and the ad8141/ ad8142 operates in its normal fashion when the disable input is driven to its low state. an unavoidable common-mode glitch occurs at the outputs when switching between disabled and enabled states and vice versa. the glitch lasts for a few tens of nanoseconds and is on the order of 2 v or 3 v. if the disable feature is used, it is recommended that common-mode protection be used on the receiver (see the ad8143 data sheet for a detailed description of common-mode protection) 09461-042 ad8142 + ? 49.9 ? 1k? 38.3 ? 80.6 ? 0.76v 0.52v 1k? 2k? +5v 2k? 100 ? 100? utp 49.9 ? 0.7v 1.5v 2.2v 1.5v 1.5v 0.8v 0.7v 0v 75? video source 1.4v 1.5v 0.8v 2.2v 0.5v ad8142 key sign a l levels on single +5v supply ad8142 output signal levels including common-mode h sync pulses figure 44. ad8142 key signal levels on single 5 v suppl y; upper drawing shows schematic, and lower drawing shows output signals with h sync pulses
ad8141/ad8142 rev. 0 | page 21 of 24 09461-043 ad8142 + ? 49.9 ? 1k? 38.3 ? 80.6 ? ?0.10v ?0.34v 1k? 2k? +2.5v ?2.5v 2k? 100 ? 100? utp 49.9 ? 0.7v ?1.0v ?0.3v ?1.0v ?1.0v ?1.7v 0.7v 0v 75? video source 1.4v ?1.0v ?1.7v ?0.3v 0.5v ad8142 key sign a l levels on single 2.5v supplies ad8142 output signal levels including common-mode h sync pulses figure 45. ad8142 key signal levels on 2.5 v supplies; upper drawing shows schematic, and lower drawing shows output signals with h sync pulses driving multiple outputs the ad8141 / ad8142 can drive four parallel utp cables (50 differential load) with only 1.5% reduction in output swing (see figure 46 ). as is expected, driving fewer parallel cables results in less output swing reduction. 09461-046 49.9 ? 100 ? utp 49.9 ? 100? 49.9 ? 100 ? utp 49.9 ? 100? 49.9 ? 100 ? utp 49.9 ? 100? 49.9 ? 100 ? utp 49.9 ? 100? ad8141/ad8142 + ? v ocm figure 46. driving four utp cables in parallel video sync-on-comm on-mode (ad8142) in computer video applications, the horizontal and vertical sync signals are most often separate from the video information signals. for example, in typical computer monitor applications, the red, green, and blue (rgb) color signals are transmitted over separate cables, as are the vertical and horizontal sync signals. when transmitting these types of video signals over long distances on utp cable, it is desirable to reduce the required number of physical channels. one way to do this is to encode the vertical and horizontal sync signals as weighted sums and differences of the output common-mode signals. the rgb color signals are each transmitted differentially over separate physical channels. the fact that the differential and common-mode signals are orthogonal allows the rgb color and sync signals to be separated at the channels receiver. cat-5 type cable contains four balanced twisted-pair physical channels that can support both differential and common-mode signals. transmitting typical computer monitor video over this cable can be accomplished by using three of the twisted pairs for the rgb and sync signals. each color is transmitted differentially, one on each of the three pairs. the encoded sync signals are transmitted among the common-mode signals of each of the three pairs. to minimize emi from the sync signals, the common- mode signals on each of the three pairs produced by the sync encoding scheme induce electric and magnetic fields that, for the most part, cancel each other. a conceptual block diagram of the sync encoding scheme is presented in figure 47 . because the ad8142 has the sync encoding scheme implemented internally, the user simply applies the horizontal and vertical sync signals directly to the appropriate inputs. as described in the theory of operation section, the ad8142 accepts ground-referenced logic- level sync pulses (see table 1 for the exact levels). in many cases, the sync pulses can be applied directly from video card vga connector outputs.
ad8141/ad8142 rev. 0 | page 22 of 24 ad8142 + ? v ocm 1k ? 2k ? 2k ? 1k ? r + ? v ocm 1k ? 2k ? 2k ? 1k ? g 2 + ? v ocm 1k ? 2k ? 2k ? 1k ? b +in r ?out r +out r ?out g +out g ?out b +out b ?in r v sync h sync sync level +in g ?in g +in b ?in b dis 09461-047 v ocm weighting equations on +5v supply: red v ocm = (v sync ? h sync ) + 1.5v green v ocm = (?2v sync ) + 1.5v blue v ocm = (v sync + h sync ) + 1.5v k 2 k 2 k 2 figure 47. ad8142 conceptual sync-on-commo n-mode encoding scheme the transmitted common-mode sync signal magnitudes are scaled by applying a dc voltage to the sync level input, referenced to the negative supply. the difference between the voltage applied to the sync level input and the negative supply sets the peak deviation of the encoded sync signals about the midsupply common-mode voltage. for example, with the sync level input set at v s? + 500 mv, the deviation of the encoded sync pulses about the nominal midsupply common-mode voltage is nominally 500 mv. the equations in figure 47 describe how the v sync and h sync signals are encoded on each colors midsupply common-mode signal. in these equations, the weights of the v sync and h sync signals are 1 (that is, +1 for high, ?1 for low), and the constant, k, is equal to the peak deviation of the encoded sync signals. figure 48 shows how the sync signals appear on each common- mode voltage in a single 5 v supply application when the voltage applied to the sync level input is set to v s? + 500 mv. although the typical setting for the sync level voltage is 500 mv above the negative supply, it can be increased, if necessary, in extremely noisy environments. increasing the sync level voltage too much has the potential to produce excessive emi. ?2.5 2.5 7.5 12.5 17.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 0 40 80 120 160 200 240 280 320 360 400 sync input voltage (v) channel output common-mode voltage (v) time (ns) sync level = 0.5v r cm g cm b cm h sync v sync 09461-048 figure 48. ad8142 sync-on-common-mode signals in single 5 v application layout and power supply decoupling considerations when designing with the ad8141 and ad8142 , adhere to standard high speed printed circuit board (pcb) layout practices. a solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. amplifier-to-amplifier isolation the least amount of isolation between the three ad8142 amplifiers exists between the green and red channels (amplifier a and amplifier b for the ad8141 ). this is, therefore, viewed as the worst-case isolation, which is reflected in table 1 and the theory of operation section. exposed paddle (epad) the 24-lead lfcsp package has an exposed paddle on the underside of its body. to achieve the specified thermal resistance, it must have a good thermal connection to one of the pcb planes. the exposed paddle must be soldered to a pad on top of the board that is connected with several thermal vias to a ground plane.
ad8141/ad8142 rev. 0 | page 23 of 24 typical ad8142 5 v application circuit figure 49 illustrates a typical ad8142 application circuit on a single 5 v supply. 09461-049 + ? + ? + ? 2 b g r ad8142 123456 19 20 21 22 23 24 12 11 10 9 8 7 17 18 16 15 14 13 0.01f +5v 38.3 ? 49.9 ? 49.9 ? 49.9 ? 49.9 ? 49.9 ? 49.9 ? 38.3 ? 17.8k ? 80.6 ? 2k? 80.6 ? 38.3 ? 80.6 ? 0.01f differential blue video out differential green video out differential red video out 0.01f 0.01f 0.01f +5v +5v +5v blue video in h sync v sync green video in red video in disable ? ? ? + + + figure 49. typical ad8142 application circuit on a single 5 v supply
ad8141/ad8142 rev. 0 | page 24 of 24 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 112108-a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 1 24 7 12 13 18 19 6 2.65 2.50 sq 2.45 forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 50. 24-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-24-7) dimensions shown in millimeters ordering guide model 1 temperature package package description package option ad8141acpz-r2 ?40c to +85c 24-lead lfcsp_wq cp-24-7 ad8141acpz-rl ?40c to +85c 24-lead lfcsp_wq cp-24-7 AD8141ACPZ-R7 ?40c to +85c 24-lead lfcsp_wq cp-24-7 ad8142acpz-r2 ?40c to +85c 24-lead lfcsp_wq cp-24-7 ad8142acpz-rl ?40c to +85c 24-lead lfcsp_wq cp-24-7 ad8142acpz-r7 ?40c to +85c 24-lead lfcsp_wq cp-24-7 ad8142-evalz evaluation board 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09461-0-7/11(0)

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